`timescale 1ns/1ns
`define clk_period 4

module vision_ctrl_tb;

	reg clk;
	reg rst_n;
		// RAM 写
	reg ram_wren;
	reg [11:0]ram_wraddress;
	reg [7:0]ram_input;
		// TFT 输出
	// wire [11:0]hcount;
	// wire [11:0]vcount;
	wire TFT_HS;
	wire TFT_VS;
	wire TFT_DE;
	wire TFT_CLK;
	wire TFT_BL;
	wire [15:0]TFT_RGB;


	vision_ctrl vision_ctrl_instance0(
		.Clk(clk),
		.Rst_n(rst_n),
		// RAM 写
		// .ram_wren(ram_wren),
		// .ram_wraddress(ram_wraddress),
		// .ram_input(ram_input),
		// TFT 输出
		// .hcount(hcount),
		// .vcount(vcount),
		.TFT_HS(TFT_HS),
		.TFT_VS(TFT_VS),
		.TFT_DE(TFT_DE),
		.TFT_CLK(TFT_CLK),
		.TFT_rgb(TFT_rgb),
		.TFT_BL(TFT_BL)
	);

	initial clk = 1'b0;
	always #(`clk_period/2) clk = ~clk;
	initial begin
		rst_n = 1'b1;
		#(`clk_period)
		rst_n = 1'b0;
		#(`clk_period)
		rst_n = 1'b1;
	
		#(`clk_period * 100000);
		$stop;
	end

endmodule 
